1. Field
Embodiments of the present disclosure relate to a digital LDO (Low Drop-Out) regulator and a resistive memory device using the same, and more particularly, to a digital LDO regulator, which is capable of rapidly responding to a peak load current variation and handling a characteristic change of a resistive memory cell, and a resistive memory device using the same.
2. Description of the Related Art
Recently, the integration of circuits with various functions in one chip has required an efficient and stable supply voltage management system.
In particular, a supply voltage required for a core processor system may have a different level depending on a type of a driving operation. That is, since the driving operation of the core processor system may be divided into a plurality of sub-operations corresponding to various commands and a supply voltage may have a different level depending on a command, a supply voltage having a different level needs to be supplied at a high speed when a command is changed to another command. Thus, research has been actively conducted to develop a supply voltage management system that rapidly generates various supply voltages required for the core processor system.
Since a switching regulator uses an inductor, the switching regulator can generate supply voltages having different levels while having excellent power efficiency. However, a generation speed of the supply voltages is low. An LDO regulator can rapidly generate a supply voltage. However, the LDO regulator cannot generate a higher voltage than a given voltage and has low power efficiency. Thus, when the switching regulator is used to generate supply voltages having different levels and the LDO regulator is used to manage the supply voltages at a high speed, supply voltages required for a core processor system can be rapidly and stably supplied.
A core processor supply voltage management system causes a difference in generation speeds of supply voltages, depending on an operation type of an LDO regulator.
FIG. 1 illustrates a conventional analog LDO regulator. Since the LDO regulator uses an amplifier, a characteristic of the LDO regulator is inevitably degraded unless the LDO regulator performs a precise process. Furthermore, a supply voltage cannot be lowered using the conventional analog LDO regulator, and thus a high bandwidth must be set for a high-speed operation.
FIG. 2A illustrates a conventional digital LDO regulator that does not include an amplifier. Instead, the conventional digital LDO regulator includes a controller and a main switching unit. The controller includes a comparator and a shift register. The main switching unit supplies a load current and includes a plurality of small transistors.
The conventional digital LDO regulator of FIG. 2A has a smaller output ripple than a digital LDO regulator using only a comparator. As illustrated in FIG. 2B, an output of the conventional digital LDO regulator reaches a target voltage over a plurality of steps. Thus, when the load current varies, a fluctuation of a load voltage is recovered at a low speed.
FIG. 3A illustrates another conventional digital LDO regulator, which includes a switching unit for supplying a load current. The switching unit includes a high-current transistor and a low-current transistor. As illustrated in FIG. 3B, the conventional digital LDO regulator of FIG. 3A controls a transient situation using the high-current transistor when the load current varies, and controls a situation following the transient situation using the low-current transistor, thereby minimizing a ripple. However, such a configuration may cause a time delay while an operation is performed by switching from the high-current transistor to the low-current transistor, and may also have a limitation in shortening the time delay.